近日，山西大学的韩拯及其研究团队取得一项新进展。经过不懈努力，他们实现二维互补逻辑的范德华极性工程化三维集成。相关研究成果已于2024年5月29日在国际权威学术期刊《自然》上发表。

该研究团队表明，通过将过渡金属二硫族化合物，如MoS₂，置于范德华(vdW)反铁磁绝缘体氯化铬(CrOCl)上，MoS₂中的载流子极性可以通过强vdW界面耦合很容易地从n型重构为p型。由此产生的能带对齐产生的晶体管室温空穴迁移率高达约425cm²V^-1s^-1，开/关比达到106，空气稳定性能超过一年。

基于这一方法，研究人员进一步成功展示了垂直构建的互补逻辑电路，包括由6层vdW材料构成的逆变器、14层vdW材料的NANDs和SRAMs。这种极性工程化的p型和n型二维半导体通道（无论是否包含vdW嵌入层）均展现出强大的鲁棒性，且适用于多种材料，为未来基于二维逻辑门的三维垂直集成电路的发展提供了宝贵的启示。

据悉，二维(2D)半导体的垂直三维集成具有很大的前景，因为它提供了在z轴上扩展逻辑层的可能性。事实上，用这种混合维异质结构以及不同载流子类型的异质- 2D层构建的，垂直互补场效应晶体管(CFETs)最近已经得到了证明。然而，到目前为止，缺乏一种可控的掺杂方案(特别是在二维半导体中以稳定和无损的方式p掺杂- WSe₂和MoS₂)，极大地阻碍了互补逻辑电路的自下而上缩放。

附：英文原文

Title: Van der Waals polarity-engineered 3D integration of 2D complementary logic

Author: Guo, Yimeng, Li, Jiangxu, Zhan, Xuepeng, Wang, Chunwen, Li, Min, Zhang, Biao, Wang, Zirui, Liu, Yueyang, Yang, Kaining, Wang, Hai, Li, Wanying, Gu, Pingfan, Luo, Zhaoping, Liu, Yingjia, Liu, Peitao, Chen, Bo, Watanabe, Kenji, Taniguchi, Takashi, Chen, Xing-Qiu, Qin, Chengbing, Chen, Jiezhi, Sun, Dongming, Zhang, Jing, Wang, Runsheng, Liu, Jianpeng, Ye, Yu, Li, Xiuyan, Hou, Yanglong, Zhou, Wu, Wang, Hanwen, Han, Zheng

Issue&Volume: 2024-05-29

Abstract: Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures, as well as hetero-2D layers with different carrier types, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe₂and MoS₂ in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS₂, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS₂ can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425cm²V^-1s^-1, on/off ratios reaching 10⁶ and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

DOI: 10.1038/s41586-024-07438-5

Source: https://www.nature.com/articles/s41586-024-07438-5