近日，湖南大学的刘渊及其研究团队取得一项新进展。经过不懈努力，他们通过范德华层压实现单片三维逐层集成。相关研究成果已于2024年5月22日在国际权威学术期刊《自然》上发表。

该研究团队提出一种替代的低温M3D集成方法，即对整个预制电路层进行范德瓦尔斯(vdW)层压，其中加工温度控制在120°C。经过进一步的逐层vdW层压工艺迭代，M3D集成系统在垂直方向上堆叠了多达10个电路层，成功突破了先前的热预算限制。详尽的电气特性测试表明，在顶部重复层压vdW电路层后，底部的2D晶体管性能未受影响。此外，利用vdW层间的通孔，可以垂直连接不同层内的器件，构建出各种逻辑和异构结构，满足系统所需的各种功能。这项研究为制造层数更多的M3D电路提供了一条低温工艺路径。

据悉，二维(2D)半导体由于其无悬键表面和能够集成到各种衬底上而没有传统的晶格匹配约束，因此在单片三维(M3D)集成方面显示出巨大的潜力。然而，由于其原子薄的体厚，2D半导体在微电子领域的高能工艺中表现出不兼容性，这使得多个2D电路层的M3D集成面临巨大挑战。

附：英文原文

Title: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Author: Lu, Donglin, Chen, Yang, Lu, Zheyi, Ma, Likuan, Tao, Quanyang, Li, Zhiwei, Kong, Lingan, Liu, Liting, Yang, Xiaokun, Ding, Shuimei, Liu, Xiao, Li, Yunxin, Wu, Ruixia, Wang, Yiliu, Hu, Yuanyuan, Duan, Xidong, Liao, Lei, Liu, Yuan

Issue&Volume: 2024-05-22

Abstract: Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120°C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

DOI: 10.1038/s41586-024-07406-z

Source: https://www.nature.com/articles/s41586-024-07406-z